1. Field of the Invention
The present invention relates to high-voltage devices and, more particularly, to an improved high-voltage metal-oxide-semiconductor (MOS) transistor device, which is capable of withstanding a higher breakdown voltage and increasing saturation drain current (IDS) thereof.
2. Description of the Prior Art
In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance.
Double diffuse drain (DDD) technology has been extensively applied to the source/drain (S/D) in order to provide a higher breakdown voltage. The DDD structure suppresses the hot electron effect caused by the short channel of the MOS transistor to further avoid electrical breakdown of the source/drain under high operational voltages. LDMOS transistors are particularly prevalent because they can operate with a high efficiency and their planar structure allows for easy integration on a semiconductor die with other circuitry.
FIG. 1 is a schematic, cross-sectional diagram illustrating a prior art symmetric high-voltage NMOS device. The high-voltage NMOS device 10 is formed in a P substrate 12. A gate electrode 22 is formed on the P substrate 12. A gate dielectric layer 24 is interposed between the gate electrode 22 and the substrate 12. A first isolation region 32 is formed between an N+ source/drain region 34 and the gate electrode 22. Two spaced-apart N type drift ion wells 36 are provided in the P substrate 12 to encompass the N+ source/drain region 34 and the first isolation region 32. A channel region 40 is located between the two spaced-apart N type drift ion wells 36. A second isolation region 38 is formed on a side of the source/drain region 34 opposite to the first isolation region 32 for isolating the high-voltage NMOS device 10 from other devices.
One approach to increasing the breakdown voltage of the above-described high-voltage NMOS device 10 is reducing the dopant concentration of the N type drift ion wells 36 and/or the dopant concentration of the N+ source/drain region 34. This is disadvantageous because reducing the dopant concentration of the ion wells leads to low saturation drain current (IDS). Another approach to increasing the breakdown voltage of the above-described high-voltage NMOS device 10 is increasing the distance between the drain 34 and the gate electrode 22. However, this will consume more chip real estate.
In light of the above, there is need in this industry to provide a high-voltage MOS transistor that can withstand higher breakdown voltage without increasing the chip size or reducing saturation drain current (IDS).